Modern microprocessors implement a variety of techniques to increase speed and save power in the performance of instruction execution. One of such techniques is branch prediction. A branch predictor may save power and increase processor speed by predicting the branch to be taken in response to an instruction. A typical branch predictor may take more than one clock cycle to generate a prediction for a subject chunk that includes an instruction. During the second and subsequent cycles of processing an instruction through the branch predictor, the first stage of the fetch machine pipeline may continue reading the next sequential chunk, on the assumption that no branch will be taken from the subject chunk being processed in the branch predictor. If a branch is predicted, the next sequential chunk that had been read into the branch predictor can be flushed, and the fetch can resume with the predicted target branch. In that case, the reading of the next sequential chunk into the first stage of the branch prediction unit that had been undertaken before a prediction was delivered will have been unnecessary, and hence, a waste of power.